Embodiments of the present inventive concept relate to semiconductor devices, and more particularly to NAND flash memory devices and memory systems including same.
NAND flash memory devices typically include a cell region and a peripheral circuit region. The cell region of a NAND flash memory device includes a memory cell array arranged in a number of blocks. In contrast, the peripheral circuit region includes a plurality of page buffer units arranged to form a page buffer. A plurality of bit lines within the NAND flash memory device extend from the cell region to the peripheral circuit region, and respectively connect some portion of the memory cell array with one or more the plurality of page buffer units.
In a conventional NAND flash memory, the separating “pitch” between adjacent ones of the plurality of bit lines, (i.e., the spacing interval between two neighboring bit lines) is very narrow. Accordingly, various electrical contacts (such as those connecting page buffer units) formed in relation to each one of the plurality of bit lines must be very carefully laid-out and fabricated. Misaligned, poorly laid-out, and/or oversized contacts may extend across neighboring bits lines and cause circuit malfunctions. Unfortunately, the narrower the separation pitch between the plurality of bit lines, the more likely this type of contact structure formation failure becomes in contemporary NAND flash memory devices. Accordingly, the design and fabrication of contacts in relation to the plurality of bits lines in NAND flash memory devices remains area of careful consideration, and this is particularly true in relation to the contact area(s) between the plurality of bit lines and the plurality of page buffer units.